NED University of Engineering & Technology

BE Computer Systems Engineering

Pipelined Implementation of Baseline JPEG Encoder

Abstract:

In this report, we describe the design and implementation of a fully pipelined architecture for implementing the JPEG baseline image compression standard. The architecture exploits the principles of pipelining and parallelism in order to obtain high speed and throughput. The design was synthesized to Altera FLEX10K series FPGAs, and synthesis was carried out using Altera Max+PlusII environment. It has been estimated that the entire architecture can be implemented on a single FPGA to yield a clock rate of about 20 MHz which would allow an input rate of 20 mega samples per second.